The present invention relates to a system formed of a large scale integration circuit (hereinafter referred to as "LSI system"), and more particularly to an LSI system which can read out detailed information on the internal status of the system without requiring any additional address signal.
An LSI system such as a microcomputer is often provided with status registers which store information reflecting various kinds of internal status of the system such as error information indispensable for program debugging or system debugging. In this case, respective outputs of the status registers may be multiplexed, as shown in FIG. 1.
FIG. 1 shows a first example of conventional LSI systems which is described, for example, on pages 378 and 379 of HITACHI MICROCOMPUTER DATA BOOK. As shown in FIG. 1, this first example includes status registers 11 and 12, a selector 15, an output buffer 16, and various kinds of registers 10, 13 and 14. In the first example, ordinary information on the internal status of the system is stored in the status register 11 (that is, a status register--A), and error information is stored in the status register 12 (that is, status register--B). The outputs of the status registers 11 and 12 are multiplexed together with the outputs of the registers 10, 13 and 14, and a desired one of these outputs is selected by a corresponding one of address signals AD. Accordingly, when an additional status register is provided in the system, an additional address signal is required for specifying the additional status register.
FIG. 2 shows a second example of conventional LSI systems which is described, for example, on pages 582 and 583 of HITACHI MICROCOMPUTER DATA BOOK. As shown in FIG. 2, the second example includes a status register (SR) 21, an error status register (ESR) 22, various kinds of registers 20, 23 and 24, a selector 25, an output buffer 26, and an OR circuit 27. In this second example, ordinary information on the internal status of the system is stored in the status register 21, and various error information is stored in the error status register 22. All the bits of the register 22 are connected to the input side of the OR circuit 27, the output side of which is connected to one bit of the status register 21. Thus, the contents of the error status register 22 are reflected on one bit of the status register 21. The outputs of the status register 21 and the error status register 22 are multiplexed together with the outputs of the registers 20, 23 and 24, and a desired one of these outputs is selected by a corresponding one of address signals AD. Accordingly, the presence of an error in the system can be detected by monitoring the status register 21, and detailed error information can be obtained in such a manner that the contents of the error status register 22 are selectively read out by an address signal. Similarly to the first example, the second example has the following drawbacks. That is, when an additional status register is provided in the system, an additional address signal is required for specifying the additional status register, and thus the number of pins connected to external address signal lines is increased.
As an LSI system becomes larger in scale and more multi-functional, it is necessary to monitor as much information on the internal status of the LSI system as possible, thereby keeping short a time necessary for system debugging. Accordingly, there arises a serious problem that external address signal lines corresponding to status registers which are provided in the system, have to be connected to the LSI system.